1. Field of the Invention
The present invention relates to a semiconductor memory device which has an array of memory cells arranged in rows and columns, each memory cell comprising a variable resistor element accompanied with a selecting transistor for storing a data by changing its electrical resistance in response to application of a voltage.
2. Description of the Related Art
Such a nonvolatile semiconductor memory device, namely a flash memory, has widely been utilized as a small-sized, mass data recording medium in a wide range of applications including a computer, a communications apparatus, a measuring apparatus, an automated control apparatus, and a house-hold or personal appliance. As inexpensive and larger in the storage size, the nonvolatile semiconductor memory device is now higher in the market demand. The reason may be that the semiconductor memory device is capable of electrically erasing and programming a data and nonvolatile for holding the data when it has been disconnected from the power source, hence functioning as a memory card arranged easily portable or a data storage or program storage provided in a mobile telephone or any other apparatus for saving nonvolatile data as the initial settings.
One type of the memory cells for use in a flash memory is known an ETOX memory cell. As shown in FIG. 15, an ETOX flash memory cell denoted by 8 has a source 3 and a drain 2 provided in a semiconductor substrate 1 thereof, which is arranged of a conducting type opposite to that of the semiconductor substrate 1, and a gate insulating layer 4 provided between the source and the drain. A floating gate 5, an interlayer insulating layer 6, and a control gate 7 are provided on the gate insulating layer 4.
According to the action principle of the flash memory cell 8, a source voltage Vs at a low level (for example, 0 V), a drain voltage Vd at a high level (for example, 6 V), and a high control voltage Vpp (for example, 12 V) are commonly applied to the source 3, the drain 2, and the control gate 7, respectively for starting a data programming action. In response, hot electrons and hot holes are produced between the drain and the source. The hot holes flow as a substrate current into the substrate while the hot electrons are injected to the floating gate, whereby the threshold voltage monitored from the control gate 7 in the transistor will increase.
For the reading action, the source voltage Vs at a low level (for example, 0 V), the drain voltage Vd at a slightly higher level than the source voltage (for example, 1 V), and the control voltage Vpp at 5 V are applied to the source 3, the drain 2, and the control gate 7, respectively. At the time, the programmed memory cell and the not programmed memory cell are different from each other in the threshold voltage and their current flowing between the source and the drain will be unequal. Accordingly, it can be judged by detecting a difference between the two currents whether the memory cell to be examined has been programmed or not. Assuming that the data is “1” and “0” when the current flowing between the source and the drain is greater and smaller respectively than a reference level, the programming and reading of two-level data can be enabled.
For the erasing action, the source voltage Vs at a high level (for example, 12 V) and the control voltage at a low level (or example, 0 V) are applied to the source 3 and the control gate 7 respectively while the drain remains at a floating state. Accordingly, a Fowler-Nordheim current runs across a tunnel oxide layer 4 between the floating gate and the source, permitting the electrons to be drawn from the floating gate 5 and thus declining the threshold voltage monitored from the control gate 7 in the transistor.
This is followed by a verifying action which is a sort of the read action for examining whether the memory cell subjected to the programming action or erasing action according to the action principle is held higher or lower than a relevant threshold voltage. For verifying the completion of the programming action, the threshold voltage of the memory cell to be subjected to the programming action is compared with that of a first reference cell where the threshold voltage (Vthp) is at higher level (for example, 5.3 V). When its threshold voltage is higher than the threshold voltage (Vthp) of the first reference cell, the memory cell is judged that it has been subjected to the programming action. For verifying the completion of the erasing action, the threshold voltage of the memory cell to be subjected to the erasing action is compared with that of a second reference cell where the threshold voltage (Vthe) is at lower level (for example, 3.1 V). When its threshold voltage is lower than the threshold voltage (Vthe) of the second reference cell, the memory cell is judged that it has been subjected to the erasing action.
FIG. 16 illustrates an arrangement of the flash memory where the memory cells 8 having the structure shown in FIG. 15 are arrayed in rows and columns and connected at the source to a common source line SL thus to form a memory cell array 10 accompanied with peripheral circuits.
The memory cell array 10 includes an m number of word lines WL1 to WLm extending along the rows and an n number of bit lines BL1 to BLn extending along the columns. The memory cells 8 at each row are connected at the control gate to a common word line while the memory cells 8 at each column are connected at the drain to a common bit line. All the memory cells 8 in the memory cell array 10 are connected at the source to the common source line SL. A row decoder 11 is connected to one end of each of the word lines WL1 to WLm while a column decoder 12 is connected to one end of each of the bit lines BL1 to BLn. The source line SL is connected with an erase circuit 13.
The row decoder 11 is arranged to receive a row address signal and an erase signal while the column decoder 12 is arranged to receive a data signal and a column address signal. The erase circuit 13 is arranged to receive the erase signal. It is assumed that the memory cell array 10 includes the m number of word lines WL1 to WLm (for example, m=2048) and the n number of bit lines BL1 to BLn (for example, n=512), and the n number of the memory cells 8 are connected at the control gate to each word line. Accordingly, the memory cell array has a memory size of m×n bits (for example, 1 Mbits). For the erasing action, the erase signal is applied to the erase circuit 13 and the row decoder 11. More particularly, the high voltage Vpp is applied to the sources of all the memory cells 8 in the matrix shown in FIG. 16 from the source line SL while all the word lines WL1 to WLm remain at the low voltage (for example, 0 V) and all the memory cells 8 can thus be erased at once.
In an actual practice, the erasing action is carried out at a block, for example, 64 Kbytes, which is relatively a large unit of data. However, the memory cells in each block to be erased may remain at the programmed state and the erased state. It is hence necessary for conducting the erasing action to use such an intricate algorithm as shown in FIG. 17.
The procedure of the erasing action shown in FIG. 17 will be explained. The erasing action starts with all the memory cells in one target block shifted to the programmed state by a common programming (channel hot electron (CHE) writing) technique (Step S1). Then, the verifying action follows for examining whether or not the threshold voltage of the memory cells subjected to the programming action at Step S1 is equal to or higher than 5.5 V, for example, in each 8-bit unit (Step S2). When the threshold voltage of the memory cells is not equal to or higher than 5.5 V, the procedure returns back to Step S1 and repeats its programming action over the memory cells. When the threshold voltage of all the memory cells is equal to or higher than 5.5 V, the procedure advances to Step S3. At Step S3, the erase voltage of a pulsed form is applied with the entire block for drawing the electrons to the source side and thus declining the threshold voltage to erase the memory cells. It is then examined at Step S4 for the erase verifying action whether or not the threshold voltage of all the memory cells in the target block is equal to or lower than 3.5 V. When the threshold voltage of the memory cells is not equal to or lower than 3.5 V, the procedure returns back to Step S3 and repeats the erasing action. When the threshold voltage is equal to or lower than 3.5 V, the procedure is terminated.
As understood from the procedure of the erasing action shown in FIG. 17, a profile of distribution of the threshold voltages after the erasing action appears as tight as possible or narrowed in the range while all the memory cells have been shifted to the programmed state at Step S1 for eliminating the over-erased state of the memory cells (where the threshold voltage is equal to or lower than 0 V). The programming action may be conducted by a common programming technique over, for example, eight of the memory cells at once. Assuming that the time required for programming one memory cell is two microseconds, the overall programming action at Step S1 takes 131 milliseconds as is denoted by Equation 1.2 μs×64 Kbytes÷8 bits=131 ms  (1)
The time required for the programming action is about 20% when the overall time required for the erasing action is 600 milliseconds. Also, assuming that the time required for reading each memory cell is 100 nanoseconds, the verifying action on the 8-bit basis at Step S2 is 6.6 milliseconds as denoted by Equation 2.100 ns×64 Kbytes÷8 bits=6.6 ms  (2)
Furthermore, the application of the pulsed erase voltage at Step S3 takes substantially 300 milliseconds.
In the procedure for the erasing action shown in FIG. 17, the time required for applying the pulsed erase voltage may be minimized by increasing the voltage applied to the source. When the source voltage is increased, the tunnel current between bands will be large enough to trap the holes in the tunnel oxide layer thus declining the reliability. Since the increase of the source voltage is unfavorable, the erasing action will hardly be speeded up.
One of the mostly known appliances equipped with the flash memories is a mobile telephone. As mobile telephones have significantly been demanded for being minimized in the dimensions, their power sources are strictly limited in the capacity and the flash memories are much preferable of a nonvolatile type which needs no backup power source for holding data during the considerable length of standby period. In addition, as the flash memories have been increased in the storage size, they allow a variety of application programs and data to be saved and selectively used thus contributing to the multi-functional performance of every mobile telephone.
Meanwhile, such known nonvolatile semiconductor memory devices including flash memories have been improved in the technology, for example, as disclosed in U.S. Pat. No. 6,204,139 by S. Liu, A. Ignatiev, et al. at the University of Houston, U.S.A. or in the report “Electric-pulse-inducted reversible Resistance change effect in magnetoresistive films” by Liu, S. Q, et al., Applied Physics Letter, Vol. 76, pp. 2749-2751, in 2000, where the pulsed voltage is applied to a perovskite material, which has an effect of super magneto-resistance, to vary the electric resistance positively and negatively. They are remarkable approaches that the resistance is varied on the order of a few digits under no presence of a magnetic field in the room temperature with the use of a perovskite material which provides a super magneto-resistive phenomenon. One of the nonvolatile, resistive memory devices where variable resistor elements utilizing the magneto-resistive phenomenon are arrayed is a resistance random access memory (RRAM) which is much lower in the power consumption than an MRAM as requiring no magnetic field and can thus highly be integrated and minimized in the overall size with much ease. In particular, as RRAM is significantly wider in the dynamic range of resistance change than MRAM, it can provide an advantageous function of multi-level storage. The actual device structure of RRAM is as extremely simple as having a lower electrode material, a perovskite metal oxide, and an upper electrode material layered from the below in this order along the vertical. More specifically in the structure disclosed in the above described U.S. Pat. No. 6,204,139, the lower electrode material is a layer of yttrium barium copper oxide (YBCO), YBa2Cu3O7, deposited on a mono-crystalline substrate of lanthanum aluminum oxide (LAO), LaAlO3, the perovskite metal oxide is a layer of crystalline praseodymium calcium manganese oxide (PCMO), Pr1-XCaXMnO3, and the upper electrode material is an Ag layer deposited by sputtering. It is reported that the memory device of that type is operable with a positive or negative pulsed voltage at 51 V applied between the upper electrode and the lower electrode thus to change the resistance. Since its action of changing the resistance positively and negatively (referred to as a “switching action” hereinafter) permits a change in the resistance to be read out, the nonvolatile semiconductor memory device becomes novel.
More particularly, the structure of the nonvolatile semiconductor memory device comprises an array of memory cells, each cell having a variable resistor element provided in the form of a PCMO layer or the like and arranged of which the electric resistance is varied for saving a data, arranged in a matrix of rows and columns thus to form a memory cell array and peripheral circuits provided about the memory cell array for controlling the action of programming, erasing, and reading the data over each memory cell.
The structure of the memory cell having a variable resistor element may be implemented by a series circuit where the variable resistor element is connected in series with its selecting transistor or by simply a variable resistor. The former memory cell is called an 1T/1R type while the latter memory cell is called an 1R type. The 1T/1R type memory cell is further classified into two forms where the bit line is connected to either the variable resistor element or the selecting transistor (for example, as disclosed in Japanese Patent Laid-open Publication No. 2004-185754 or No. 2004-185755).
For selecting the memory cell to be read, programmed, or erased in the 1T/1R type memory cell array, bias voltages are applied to the selected word line and the selected bit line to switch on the selecting transistor in the selected memory cell connected to both the selected word line and the selected bit line. More specifically, the variable transistor element in the selected memory cell is supplied with a reading current, a programming current, or an erasing current. This allows the 1T/1R type memory cell to be accompanied with peripheral circuits which are equal to those in a conventional flash memory.
It is desired that in view of application programs and data having significantly been increased in the overall size, the conventional nonvolatile semiconductor memory device is favorably systematized for upgrading its functions and correcting bugs through writing the software saved therein. The conventional types of flash memory however have a drawback that the action of writing the data consumes a considerable length of time and remains limited in the data size to be handled. Also, another drawback is to spare an extra storage area for buffering files, hence making the action of writing the data extremely complicated in steps.
The conventional nonvolatile semiconductor memory device or flash memory may be replaced by a resistive, nonvolatile memory including a variable resistor element in order to speed up the action of writing (erasing and programming) the data. The theory of writing the data of the variable resistor element (using a change in the electric resistance) is however not equal to that of the conventional nonvolatile semiconductor memory device or flash memory (involving injection and drawing out of electrons across the floating gate). Accordingly, even when the algorithm for writing employed in the conventional flash memory is applied to the resistive nonvolatile memory including the variable resistor element, the speeding up expected for each memory cell will not necessarily be expected in the whole device.